High-k dielectric materials are dielectric materials having a dielectric constant (k) greater than that of silicon nitride (i.e., k>about 7). High-k dielectric materials are currently being considered and/or implemented for next generation integrated circuit applications, such as: (a) gate dielectric material to replace SiO2 in advanced metal-oxide-semiconductor field-effect transistor (MOSFET) structures; (b) dielectric material in a capacitor structure of a DRAM device; and (c) dielectric in a capacitor structure of non-volatile ferroelectric RAM (FeRAM) devices, for example.
FIGS. 1–3 illustrate current processes for patterning a high-k dielectric layer 20 for the case where a high-k dielectric material is used as a gate dielectric for a MOSFET structure. FIG. 1 shows an initial unpatterned structure 22 having a gate conductor layer 24 (e.g., metal) over a high-k dielectric layer 20, which is over a substrate 26 (e.g., silicon). Typically, it is preferred to use a dry etch process (e.g., reactive ion etching, ion milling) for etching the gate conductor layer 24, e.g., to provide good profile and critical dimension control.
The methods of wet etching alone and dry etching alone to remove high-k dielectric material often do not provide high etch selectivity with respect to the underlying substrate 26. As a result these methods are likely to recess the substrate 26, as shown in FIG. 2, or damage the substrate 26, as shown in FIG. 3 (see damage areas 28). The recess of the substrate 26 (see e.g., FIG. 2) after etching the high-k dielectric layer 20 may have a depth 30 of about 11 to 12 nm, for example. Avoiding recess of the substrate 26 by stopping the dry etching sooner often causes damage 28 to the substrate 26, as illustrated in FIG. 3, which may cause problems for subsequent silicide formation, for example. Hence, there is a need for a method of removing the high-k dielectric material without these drawbacks.